1. Field of the Invention
The present invention relates to a pattern correction method, an exposure mask, a manufacturing method of an exposure mask, and a manufacturing method of a semiconductor device.
2. Description of Related Art
Generally, a semiconductor integrated circuit device has plural transistors as component elements. For example, in a memory cell of an SRAM (Static Random Access Memory), many field-effect transistors forming pairs (hereinafter, a pair of transistors is also referred to as “paired transistors”) on the circuit are used. More specifically, a one-port SRAM cell having a CMOS (Complementary Metal Oxide Semiconductor) configuration has three kinds of paired transistors having different functions such as drive transistors, transfer transistors, and load devices.
In the case where plural transistors are provided as component elements, it is considered that there may be characteristic differences among paired transistors due to occurrence of pattern displacement, pattern distortion, or the like in a semiconductor manufacturing process, for example. Such characteristic differences should be prevented because there is a possibility that the flip-flops may become imbalanced and it may be difficult to secure the stability of cell operation. On this account, regarding a semiconductor integrated circuit device, it has been proposed that a diffusion layer forming the transistor is formed in a simple rectangular shape for reduction of influence of displacement or the like (e.g., see JP-A-2001-28401). Further, it has been also proposed that, even when displacement occurs, the pattern shape is changed so that the shapes of paired transistors may be the same (e.g., see JP-A-8-241929).